A flash memory is capable of maintaining stored data without an external power supply. In addition, the flash memory can perform electrical erase and program operations freely even without additional refresh processes applied to the stored data. Since a NAND type flash memory has a string structure consisting of a plurality of flash memory cells connected in serial, the NAND type flash memory is suitable for a high integration and widely used in portable electronic apparatuses as a data storage.
With rapidly increasing use of data requiring large storage capacity, such as motion pictures, voices and graphics, the NAND type flash memory having high integration density has been more widely used.
The NAND type flash memory is characterized by several operation methods that draw clear line between flash memories and other memories apart from cell characteristics. One of the most critical characteristics for the NAND type flash memory in the ability to operate in the methods of a command preset and an address preset.
According to the command preset method, commands that are combinations of predetermined bits (e.g., 00h, 80h, etc.) are inputted into a chip through an I/O pin to determine a next operation. According to the address preset method, an address to read or write data is inputted into the chip directly before starting an operation.
The other memories such as SRAMs start to perform reading or writing operation of data as soon as an address and a clock for the operations are introduced. In contrast, the NAND type flash memory inputs a command to perform and an address into a chip using the above command preset method and the address preset method, and then performs the operation of reading or writing data if a clock is inputted. In the NAND type flash memory, there is clear interval between the time when data is inputted or outputted and the time when the address or command is introduced. Therefore, an input pin for introducing addresses or commands can be used in common with a data I/O pin.
FIG. 1 is a block diagram illustrating a conventional ×8 NAND type flash memory.
As shown in FIG. 1, the conventional NAND type flash memory includes a memory cell array 100, a row selection circuit 101, a column selection circuit 103, a data latch circuit 102, a control circuit 104 and a data input/output circuit 105. The memory cell array 100 is a data storage, and the row selection circuit 101 selects a row of the memory cell array 100 according to row addresses A12 to A27. The column selection circuit 103 selects a column of the memory cell array 100 according to column addresses A0 to A11. The data latch circuit 102 latches the data of the memory cell array 100. The control circuit 104 controls operations inputting/outputting the data according to inputted clock signals nWE, nRE and nCE and control signals ALE, CLE and Command.
Conventional NAND type flash memory comprises eight data I/O pins I/O0˜I/O7 coupled to the data I/O circuit 105, a plurality of clock signal nWE, nRE, nCE input pins and control signal ALE, CLE input pins. The data I/O pins I/O0˜I/O7 are used for inputting the command and the address A0˜A27 and for inputting/outputting data. The clock signal nWE, nRE, nCE input pins control memory operations, and the control signal ALE, CLE input pins determine a kind of the data inputted into the data I/O pins I/O0˜I/O7. The clock signal nWE is used for a synchronization of the addresses, commands and data introduced in the memory. The clock signal nRE is used for a synchronization at the time of data read out, and the clock signal nCE is used for selecting an operation of memory chip. The address latch enable (ALE) signal is a control signal used for identifying the data transferred through the data I/O pins I/O0˜I/O7 as an address. The command latch enable (CLE) signal is a control signal used for identifying the data transferred through the I/O pins I/O0˜I/O7 as a command.
Conventionally, the command comprises 8-bits, such that the command may be inputted into the memory in one cycle, but the address comprises more than 8-bits, such that it is needed more than one cycle to input all the address as shown in the following Table 1.
TABLE 1CycleI/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 71stA0A1A2A3A4A5A6A72ndA8A9A10A11LLLL3rdA12A13A14A15A16A17A18A194thA20A21A22A23A24A25A26A27
The address A0˜A11 in Table 1 is a column address for selecting a column of a memory cell array, and the address A12˜A27 is a row address for selecting a raw. In addition, the signal introduced through the data I/O pins I/O4˜I/O7 is usually set to a low level.
Meanwhile, if the number of the I/O pins is increased to sixteen and the device operates at a ×16 speed, data being inputted or outputted in parallel becomes doubled and the time (cycles) for processing the same number of data decreases to half. Therefore, efficiency of inputting/outputting data can be doubled over ×8 operation. The following Table 2 describes inputs of the address when the memory operates at a ×16 speed.
TABLE 2I/O 8˜CycleI/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7I/O 151stA0A1A2A3A4A5A6A7L2ndA8A9A10LLLLLL3rdA11A12A13A14A15A16A17A18L4thA19A20A21A22A23A24A25A26L
As described in Table 2, even if the number of I/O pins is 16, only 8 pins I/O 0˜I/O 7 are used for inputting the address. The I/O pins I/O 8˜I/O 15 are used only in inputting/outputting data and usually set to a low level during the input of address. One (i.e., I/O 3 in second cycle) of the addresses used in the case of the ×16 speed operation decreases compared to the case of the ×8 speed operation because the number of data applied in serial decreases to half its number.
As explained above, the ×16 speed memory has double efficiency compared to the ×8 speed memory. However, ×8 or ×16 memory is selectively used in a process of fabricating products according to functions and needs of the products regardless of the input/output efficiency. Therefore, most enterprises fabricating memories produce both of ×8 and ×16 memories. However, the ×8 nonvolatile semiconductor memory and the ×16 nonvolatile semiconductor memory regime different fabrication processes. Therefore, the fabrication process may be inefficient.